Bridging the Gap Between Layout Pattern Sampling and Hotspot Detection via Batch Active Learning

Layout hotpot detection is one of the main steps in modern very-large-scale-integration (VLSI) chip design. A typical hotspot flow extremely time consuming due to computationally expensive mask optimization and lithographic simulation. Recent researches try facilitate procedure with a reduced flow, including feature extraction, training set generation, detection, where extraction methods engines are deeply studied. However, performance detectors relies highly on quality reference layout libraries which costly obtain usually predetermined or randomly sampled previous works. In this article, we propose an active learning-based pattern sampling simultaneously optimizes machine-learning model that aims achieve similar better much smaller number instances. Experimental results show our proposed method can significantly reduce lithography simulation overhead while attaining satisfactory accuracy designs under both DUV EUV technologies.